Design and FPGA Implementation of Compositional Microprogram FIR Filter

Abstract

FIR Filters on Field Programmable Gate Array (FPGA) are designed by different methods of Digital Design. Microprogramming based FIR filters are vastly used in Video and Image Processing application. Purpose technique is Compositional Microprogram Control Unit (CMCU) FIR Filter. CMCU is both time and area optimized filter than that of microprogram FIR Filter. Parallel architecture is used in Data path of design. Verilog Hardware Descriptive Language (HDL) is used to implement design. Results are evaluated on ModelSim SE Plus 6.1f and hardware optimization results are evaluated on Xilinx ISE web pack 10.1. As an example of synthesis, Compositional Microprogram Control Unit (CMCU) FIR Filter designed in this paper is also tested for real time Audio Filtering. Code is tested on FPGA XC3S700AN [14] using stereo audio codec (AKM AK4551) [13] on 50MHz clock frequency. Proposed filter is tested for third order but it can be extended for higher order which can be used for high speed applications like DSP applications e.g., Noise Cancelation, Video and Image Processing.
Index Terms— FPGA, Compositional Microprogram,